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NT7501
33 X 100 RAM-Map LCD Controller/Driver
Features
! Direct RAM data display using the display RAM. When RAM data bit is 0, it is not displayed. When RAM data bit is 1, it is displayed. (In normal display mode) ! RAM capacity: 65 X 132 = 8580 bits ! Many command functions: Read/Write Display Data, Display ON/OFF, Normal/Reverse Display, Page Address Set, Set Display Start Line, Set LCD Bias, Electronic contrast Controls, Read Modify Write, Select Segment Driver Direction and Power Save ! High-speed 8-bit microprocessor interface allowing direct connection to both the 8080 and 6800 ! Serial interface ! Single supply operation, 2.4 - 3.5V ! Maximum 9V LCD driving output voltage ! 2X / 3X / 4X on chip DC-DC converter ! Voltage regulator ! Voltage follower (LCD bias: 1/5 or 1/6) ! On chip oscillator
General Description
The NT7501 is a single-chip LCD driver for dot-matrix liquid crystal displays, which is directly connectable to a microcomputer bus. It accepts 8-bit serial or parallel display data directly sent from a microcomputer and stores it in an on-chip display RAM. It generates a LCD drive signal independent of the microprocessor clock. The set of the on-chip display RAM of 65 X 132 bits, and a one-to-one correspondence between the LCD panel pixel dots and the on-chip RAM bits, permits implementation of displays with a high degree of freedom. As a total of 133 circuits of common and segment outputs are incorporated, a single chip of NT7501 can make 33 X 100 dots displays. No external operation clock is required for RAM read/write operations. Accordingly, this driver can be operated with minimum current consumption and its on-board low-currentconsumption liquid crystal power supply can implement a high-performance handy display system with minimal current consumption and a minute LSI configuration.
1
V2.0
NT7501
Pad Configuration
197
181 180~113
114
98
198 200 211~199
97
NT7501
18~63 1 17 64 80
95 94~82
212 214
83 81
2
NT7501
Block Diagram
VDD
SEG0
SEG99 COM0 COM31 COMS
V0 V2 V3 V4 Vss TPS0 TPS1 CAP1+ CAP1CAP2+ CAP2-
Segment driver
Common driver Shift register
Power Supply Circuit
Display data latch Initial display line register
I/O buffer circuit
CAP3+
line address decoder
VOUT VR
Output status selector circuit
132*65-dot display data RAM
Column address decoder Page address register 8-bit column address counter Display timing generator circuit
FRS FR CL DYO DOF M/S
8-bit column address counter
Bus holder
Command decoder
Bus holder
Line counter
Oscillator
COM S
V1
VS1
Microprocessor interface
I/O buffer
CS1 CS2
A0
RD WR C86 (E) (R / W )
P/S RES
D6 D5 D7 (SI) (SCL)
D4
D3
D2
D1
D0
3
NT7501
Pad Description
Power Supply Pad No. 20 - 26 35 - 42 Symbol VDD VSS I/O Supply Supply Description 2.4 - 3.5V power supply input. These pads must be connected to each other Ground input. These pads must be connected to each other LCD driver supply voltages. The voltage determined by the LCD cell is impedance-converted by a resistive driver or an operation amplifier for application. Voltages should have the following relationship: V0 V1 V2 V3 V4 VSS Supply When the on-chip operating power circuit is on, the following voltages are given to V1 to V4 by the on-chip power circuit. Voltage selection is performed by the Set LCD Bias command V1 V2 V3 V4 4/5V0, 5/6V0 3/5V0, 4/6V0 2/5V0, 2/6V0 1/5V0, 1/6V0
63 - 64 65 - 66 67 - 68 69 - 70 71 - 72
V0 V1 V2 V3 V4
LCD Driver Supplies Pad No. 47 - 48 49 - 50 51 - 52 53 - 54 45 - 46 12, 61 - 62, 77 9, 15, 59 - 60, 73 - 74 43 - 44 55 - 56 57 - 58 75 - 76 Symbol CAP1CAP1+ CAP2CAP2+ CAP3+ VDD VSS VOUT V0 VR TPS0, TPS1 I/O O O O O O Supply Supply O O I I Description Capacitor 1- pad for internal DC/DC voltage converter Capacitor 1+ pad for internal DC/DC voltage converter Capacitor 2- pad for internal DC/DC voltage converter Capacitor 2+ pad for internal DC/DC voltage converter Capacitor 3+ pad for internal DC/DC voltage converter Used for pad option or to connect to power filter capacitor Used for pad option or to connect to power filter capacitor DC/DC voltage converter output Connect to Rb Voltage adjustment pad. Applies voltage between V0 and VSS using a resistive divider Selects the temperature coefficient of the reference voltage
4
NT7501
System Bus Connection Terminals Pad No. Symbol I/O Description This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus. When the serial interface is selected (P/S = "L"), then D7 serves as the serial data input terminal (SI) and D6 serves as the serial clock input terminal (SCL). At this time, D0 to D5 are set to high impedance. When the chip select is inactive, D0 to D7 are set to high impedance. This is connected to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or a command. A0 = "H": Indicate that D0 to D7 are display data. A0 = "L": Indicates that D0 to D7 are control data. When RES is set to "L", the settings are initialized. The reset operation is performed by the RES signal level. I This is the chip select signal. When CS1 = "L" and CS2 = "H", then the chip select becomes active and data/command I/O are enabled When connected to an 8080 MPU, it is active LOW. This pad is 18 RD (E) I connected to the RD signal of the 8080MPU, and the NT7501 data bus is in an output statue when this signal is "L". When connected to a 6800 Series MPU, this is active HIGH. This is used as an enable clock input of the 6800 series MPU. When connected to an 8080 MPU, this is active LOW. This terminal connects to the 8080 MPU WR signal . The signals on the data bus are 17 WR (R W ) I latched at the rising edge of the WR signal. When connected to a 6800 Series MPU: This is the read/write control signal input terminal. When R W = "H": Read. When R W = "L": Write. 14 C86 I This is the MPU interface switch terminal. C86 = "H": 6800 Series MPU interface. C86 = "L": 8080 Series MPU interface. This is the parallel data input/serial data input switch terminal. P/S = "H": Parallel data input. P/S = "L": Serial data input. The following applies depending on the P/S status:
P/S Data/Command Data Read/Write Serial Clock SCL (D6)
27 - 34
D0 - D7 (SI) (SCL)
I/O
16
A0
I
8
RES
I
11 - 13
CS1 CS2
10
P/S
I
"H" "L"
A0 A0
D0 to D7 RD WR SI (D7) Write only
When P/S = "L", D0 to D5 are HZ. D0 to D5 may be "H", "L" or Open. RD (E) and WR ( R / W ) are fixed to either "H" or "L". With serial data input, RAM display data reading is not supported. This terminal selects the master/slave operation for the NT7501 chips. Master operation outputs the timing signals that are required for the LCD display, while slave operation inputs the timing signals required for the liquid crystal display, synchronizing the liquid crystal display system. This is the display clock input terminal. When the NT7501 chips are used in master/slave mode, the various CL terminals must be connected.
7
M/S
I
4
CL
I/O
5
NT7501
System Bus Connection Terminals (continue) Pad No. Symbol I/O Description This is the liquid crystal alternating current signal I/O terminal. M/S = "H": Output M/S = "L": Input When the NT7501 chip is used in master/slave mode, the various FR terminals must be connected. 3 6 DYO VS1 O O Common drive signal output. This output is enabled for only in master operation and connects to the common driver DIO pad. It becomes HZ in slave operation. Internal power supply voltage monitor output. This is the liquid crystal display blanking control terminal. M/S = "H": Output M/S = "L": Input When the NT7501 chip is used in master/slave mode, the various DOF terminals must be connected 1 FRS O This is the output terminal for the static drive. This terminal is only enabled when the static indicator is ON when in master operation mode, and is used in conjunction with the FR terminal.
2
FR
I/O
5
DOF
I/O
Liquid Crystal Drive Pads Pad No. 98 - 197 81 - 96, 198 - 213 Symbol SEG0 - 99 COM15 - 0 COM16 - 31 I/O O O Description Segment signal output for LCD display Common signal output for LCD display These are the COM output terminals for the indicator. Both terminals output the same signal. Do not connect these terminals if they are not used. When in master/slave mode, the same signal is output by both master and slave.
97, 214
COMS
O
Option Pads Pad No. 78 - 80 Symbol OP1 - OP3 I/O I Description Internal pull high, no connection for user
6
NT7501
Functional Description
Microprocessor Interface Interface type selection The NT7501 can transfer data via 8-bit bi-directional data bus (D7 to D0) or via serial data input (SI). When high or low is selected for the parity of the P/S pad, either 8-bit parallel data input or serial data input can be selected as shown in Table 1. When serial data input is selected, the RAM data cannot be read out. Table 1. P/S H L Type Parallel Input Serial Input CS1 CS1 CS1 CS2 CS2 CS2 A0 A0 A0 RD RD WR WR C86 C86 D7 D7 SI D6 D6 SCL D0 to D5 D0 to D5 (HZ)
"-" must always be high or low
Parallel Input
When the NT7501 selects parallel input (P/S = high), the 8080 series microprocessor or 6800 series microprocessor can be selected by causing the C86 pad to go high or low as shown in Table 2. Table 2. C86 H L Type 6800 microprocessor bus 8080 microprocessor bus CS1 CS1 CS1 CS2 CS2 CS2 A0 A0 A0 RD E RD WR RW RW D0 to D7 D0 to D7 D0 to D7
Data Bus Signals The NT7501 identifies the data bus signal according to A0, E, R W ( RD , WR ) signals. Table 3. Common A0 1 1 0 0 6800 processor (R W ) 1 0 1 0 8080 processor Function RD 0 1 0 1 WR 1 0 1 0 Reads display data Writes display data Reads status Writes control data in internal register. (Command)
Serial Interface (P/S is low)
The serial interface consists of an 8-bit shift register and a 3-bit counter. The serial data input and serial clock input are enabled when CS1 is low and CS2 is high (in chip select status). When the chip is not selected, the shift register and counter are reset. The serial data of D7, D6, D0 are read at D7 in this sequence when the serial clock (SCL) goes high. They are converted into 8-bit parallel data and processed on rising edge of every eighth serial clock signal. The serial data input (SI) is determined to be the display data when A0 is high, and the control data when A0 is low. A0 is read on the rising edge of every eighth clock signal. Figure1 shows a timing chart of serial interface signals. The serial clock sign must be terminated correctly against termination reflection and ambient noise. Operation checkout on the actual machine is recommended.
7
NT7501
CS1
CS2 SI SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1
A0
Figure 1. Chip Select Inputs The NT7501 has two chip select pads, CS1 and CS2 can interface to a microprocessor when CS1 is low and CS2 is high. When these pads are set to any other combination, D0 to D7 are high impedance and A0, E and R W inputs are disabled. When the serial input interface is selected. the shift register and counter are reset. Access to Display Data RAM and Internal Registers The NT7501 can perform a series of pipeline processes between the LSI's using the bus holder of the internal data bus in order to match the operating frequency of the display RAM and the internal registers with that of the microprocessor. For example, the microprocessor reads data from the display RAM in the first read (dummy) cycle, stores it in the bus holder and outputs it onto the system bus in the next data read cycle. Also, the microprocessor temporarily stores display data in the bus holder, and stores it in the display RAM until the next data write cycle starts. When viewed from the microprocessor, the NT7501 access speed greatly depends on the cycle time rather than the access time to the display RAM (tACC). It shows the data transfer speed to/from the microprocessor can increase. If the cycle time is inappropriate, the microprocessor can insert the NOP instruction that is equivalent to the wait cycle setup. However, there is a restriction in the display RAM read sequence. When an address is set, the specified address data is NOT output at the read instruction immediately following. Instead, the address data is output only during second data read. A single dummy read must be inserted after the address setup and after write cycle (refer to Figure2).
A0 MPU E R/W
DATA Address preset Read signal Internal timing Column address
N
N
n
n+1
Preset N
Incremented N+1 N+2
BUS holder
Set address n
N
Dummy read
n
Data Read address n
n+1
n+2
Data Read address n+1
Figure 2.
8
NT7501
Busy Flag The Busy flag is set when the NT7501 starts to operate. During operation, it accepts Read Status instruction only. The busy flag signal is output at pad D7 when Read Status is issued. If the cycle time (tCYC) is correct, the microprocessor need not check the flag before issuing a command. This can greatly improve the microprocessor performance. Initial Display Line Register When the display RAM data is read, the display line, according to COM0 (usually, the top line of screen), is determined using register data. The register is also used for screen scrolling and page switching. The set Display Start Line command sets the 6-bit display start address in this register. The register data is preset on the line counter each time the FR signal status changes. The line counter is incremented by CL signal and it generates a line address to allow 132 bit. Column Address Counter This is a 8 bit presettable counter that provides the column address to the display RAM (refer to Figure4). It is incremented by 1 when a Read/Write command is entered. However, the counter is not incremented but locked if a non-existing address above 84H is specified. It is unlocked when a column address is set again. The Column Address counter is independent of the Page Address register. When the ADC Select command is issued to display an inverse display, the column address decoder inverts the relationship between the RAM column address and the display segment output. Page Address Register This is a 4-bit page address register that provides a page address to the display RAM (refer to Figure 4). The microprocessor issues Set Page Address command to change the page and access to another page. Page address 8 (D3 is high, but D2,D1 and D0 are low) is RAM area dedicated to the indicator, and only display data D0 is valid. Display Data RAM The display data RAM stores pixel data for the LCD. It is a 65-column by 132-row (8-page by 8 bit + 1) addressable array. Each pixel can be selected when the page and column addresses are specified. The time required to transfer data is very short because the microprocessor enters D0 to D7 corresponding to the LCD common lines as shown in Figure 3. Therefore, multiple NT7501's can easily configure a large display having high flexibility with very little data transmission restriction. The microprocessor writes and reads data to/from the RAM through the I/O buffer. As the LCD controller operates independently, data can be written into the RAM at the same time as the data is being displayed, without causing the LCD to flicker.
D0 D1 D2 D3 D4
1 0 1 0 1 Display data RAM
COM0 COM1 COM2 COM3 COM4 Display on LCD
Figure 3.
9
NT7501
Relationship between display data RAM and address (if initial display line is 21H)
Page Address Data
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 ADC D0= D0= "1" "0" 10 12 11
Line Address
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
D3,D2, D1,D0 0,0,0,0
Page0
0,0,0,1
Page1
0,0,1,0
Page2
0,0,1,1
Page3
COM output
Start COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COMS
0,1,0,0
Page4
0,1,0,1
Page5
0,1,1,0
Page6
0,1,1,1
Page7
1,0,0,0 Column address
Page8 71 12 SEG97 72 SEG98 11 73 SEG99 10
73 SEG0
72 SEG1
SEG2
LCD OUT
71
Figure 4.
10
NT7501
Display Timing Generator This section explains how the display timing generator circuit operates. Signal Generation to Line Counter and Display Data Latch Circuit The display clock (CL) generates a clock to the line counter and a latch signal to the display data latch circuit. The line address of the display RAM is generated in synchronization with the display clock. 100-bit display data is latched by the display data latch circuit in synchronization with the display clock and output to the segment LCD drive output pad. The display data is read to the LCD drive circuit completely independent of access to the display data RAM from the microprocessor. LCD AC Signal (FR) Generation The display clock generates an LCD AC signal (FR). The FR causes the LCD drive circuit to generate a AC drive waveform. It generates a 2-frame AC drive waveform. When the NT7501 is operated in slave mode on the assumption of multi-chip, the FR pad and CL pad become input pads. Common Timing Signal Generation The display clock generates an internal common timing signal and a start signal (DYO) to the common driver. A display clock resulting from frequency division of an oscillation clock is output from the CL pad. When an AC signal (FR) is switched, a high pulse is output as a DYO output at the turning edge of the previous display clock. Refer to Figure 5. The DYO output is output only in master mode. When the NT7501 is used for multi-chip, the slave requires to receive the FR, CL, DOF signals from the master. Table 4 shows the FR, CL, DYO and DOF status. Table 4. Model NT7501 Slave HZ denotes a high-impedance status Example of NT7501 1/33 duty (Dual-frame AC driver waveforms) Input Input HZ Input Operation mode Master FR Output CL Output DYO Output DOF Output
32
33
1
2
3
4
5
6
28
29
30
31
32
33
1
2
3
4
5
CL FR
DYO V0 V1 V4 VSS V0 V1 V4 VSS
COM0
COM1 RAM data SEGn
V0 V2 V3 VSS
Figure 5.
11
NT7501
Display Data Latch Circuit This circuit temporarily stores (or latches) display data (during a single common signal period) when it is output from display RAM to LCD panel driver circuit. This latch is controlled by Display in normal/reverse Display ON/OFF and Entire display on commands. These commands do not alter the data. LCD Driver This is a multiplexer circuit consisting of 100 segment outputs to generate four-level LCD panel drive signals. The LCD panel drive voltage is generated by a specific combination of display data, a COM scan signal, and a FR signal. Figure 5 gives an example of SEG and COM output waveform. Oscillator Circuit This is an oscillator having a complete built-in type CR, and its output is used as the display timing signal source or as the clock for the voltage booster circuit of the LCD power supply. The oscillator circuit is available in master mode only. The oscillator signal is divided and output as a display clock at the CL pad. Power Supply Circuit The power supply circuit generates voltage to drive the LCD panel at low power consumption, and is available in NT7501 master mode only. The power supply circuit consists of a voltage booster, a voltage regulator and a LCD drive voltage follower. The power supply circuit built into the NT7501 is set for a small-scale LCD panel and is inappropriate for a large-pixel panel and a large-display-capacity LCD panel using multiple chips. As the large LCD panel has the dropped display quality due to a large load capacity, it must use an external power source. The power circuit is controlled by the Set Power Control command. This command sets a three-bit data in the Power Control register to select one of eight power circuit functions. The external power supply and part of the internal power circuit functions can be used simultaneously. The following explains how the Set Power Control command works. [Control by Set Power Control command] D2 turns on when the voltage booster control bit goes high, and D2 turns off when this bit goes low. D1 turns on when the voltage regulator control bit goes high, and D1 turns off when this bit goes low. D0 turns on when the voltage follower control bit goes high, and D0 turns off when this bit goes low. [Practical combination examples] Status 1: To use only the internal power supply Status 2: To use only the voltage regulator and voltage follower Status 3: To use only the voltage follower, input the external voltage V0 Status 4: To use only an external power supply because the internal power supply does not operate External voltage input VOUT V0 V0 to V4 Voltage booster terminal Used OPEN OPEN OPEN Voltage regulator terminal Used Used OPEN OPEN
D2 1 2 3 4 1 0 0 0
D1 1 1 0 0
D0 1 1 1 0
Voltage booster ON OFF OFF OFF
Voltage regulator ON ON OFF OFF
Voltage follower ON ON ON OFF
* The voltage booster terminals are CAP1+, CAP1-, CAP2+, CAP2- and CAP3+ * Combinations other than those shown in the above table are possible but impractical.
12
NT7501
Booster Circuit If capacitors C1 are connected between CAP1+ and CAP1-, CAP2+ and CAP2-, or between CAP1- and CAP3+ and between VSS and VOUT, the potential between VDD and VSS is boosted by four times toward the positive side and it is output at VOUT. For triple boosting, remove only the capacitor between CAP1- and CAP3+ from the connection of the quadruple boosting operation and then short between CAP3- and VOUT. The triple boosted voltage appears at VOUT (CAP3+). For double boosting, remove only capacitor C1 between CAP2+ and CAP2- from the connection of triple boosting operation, open CAP2- and short between CAP2+, CAP3+ and VOUT. The double boosted voltage is output at VOUT (CAP3+, CAP2+). For quadruple boosting, set a VDD voltage range so that the voltage at VOUT may not exceed the absolute maximum rating. As the booster circuit uses signals from the oscillator circuit, the oscillator circuit must be operative.
VSS
C1
VSS
C1 NT7501
VSS
C1 NT7501
VOUT
CAP3+
VOUT
CAP3+ CAP1-
VOUT
CAP3+ CAP1NT7501
C1 C1
CAP1CAP1+ CAP2+
C1 CAP1+ CAP2+ C1 CAP2-
C1 CAP1+ CAP2+ CAP2-
C1
CAP2-
4x step-up voltage circuit
3x step-up voltage circuit
2x step-up voltage circuit
VDD = 2.4V VSS = 0V
VOUT = 3 X VDD = 9V VDD = 3V VSS = 0V
VOUT = 2 X VDD = 6V VDD2 = 3V VSS = 0V 2x step-up voltage relationships
4x step-up voltage relationships
3x step-up voltage relationships
13
NT7501
Voltage Regulator Circuit The function of the internal voltage regulator circuits is to determine the liquid crystal operating voltage V0, by adjusting resistors Ra and Rb, within the range V0 < VOUT. VOUT is the operating voltage of the operational amplifier circuits shown in Figure 6. Feedback gain control for initial LCD voltage. External resistors are connected between V0 and VR, and between VR and VSS and these resistors are chosen to give the desired V0 according to the following equation: V0 = (1 + Rb/Ra) X VREG + Rb X Iref TPS1 0 0 1 1 TPS0 0 1 0 1 Thermal Gradient (% / C) -0.05 (Internal VREG used) -0.2 (Internal VREG used) 0 0 VREG (V) 2.2 2.45 VDD VDD
Voltage Regulator Using the Electronic Volume Control Function The Electronic Volume Control Function can adjust the intensity (brightness level) of the LCD screen by electronic control command. Software controls the 32 voltage levels of V0. This yields the following equation: V0 = (1+ Rb/Ra) X VREG + Rb X Iref Where Iref = 0 to 6.5A 40% depending on the 5-bit data set by the electronic control command.
Rb
Vout
Ra Iref VREG
V0
Vss
Figure 6.
14
NT7501
Reference Power Supply Circuit for Driving LCD Panel -When using all LCD power circuits (Voltage converter regulator and follower) (In case of 3X boosting circuit)
VDD
-When not using voltage booster circuits
VDD
C1 VOUT C3+ C1 C1 Ra VR C2 C2 C2 C2 C2 Rb V0 V1 V2 V3 V4 C2+ C2C1+ C1-
M/S
External Power Supply
M/S VOUT C3+ C2+ C2C1+ C1-
Ra VR C2 C2 C2 C2 C2 Rb V0 V1 V2 V3 V4
VSS
VSS
When not using the internal LCD power supply circuits When only using voltage follower
VDD
VDD
M/S VOUT C3+
*Value of External Capacitance M/S Item C1 C2 Value 1.0~4.7 0.47~1.0 F VOUT C3+ C2+ C2C1+ C1VR V0
External Power Supply
C2+ C2C1+ C1VR
C2 C2 C2 C2 C2
V0 V1 V2 V3 V4
External Power Supply
V1 V2 V3 V4
VSS
VSS
15
NT7501
Command Sequence when Built-in Power Supply is Turned OFF To turn off the built-in power supply, follow the command sequence as shown below after setting the system to standby mode.
Static Indicator ON Display OFF Entire Display ON Built-in Power OFF
Command ADH Command AEH Command A5H
}
Power Save Command
Reset Circuit When the RES input goes low, this LSI is initialized. Initialized status 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Display OFF Normal display ADC select: Normal display (ADC command D0 = low) Read modify write OFF Power control register (D2, D1, D0) = (0, 0, 0,) Register data clear in serial interface LCD power supply bias ratio 1/6 Static indicator: OFF Display start line register set at line 1 Column address counter set at address0 Page address register set at page 0 Output status register (D3) = (0) Electronic control register set at 0 Test command OFF
As seen in Figure 8 Microprocessor Interface (Reference Example). Connect the RES pad to the reset pin of the microprocessor and initialize the microprocessor at the same time. In case the NT7501 does not use the internal LCD power supply circuit, the RES must be low when the external LCD power supply is turned on. When RES goes low, each register is cleared and set to the above initialized status. However, it has no effect on the oscillator circuit and output pads (FR, CL, DYO, D0 to D7) The initialization by RES pad signal is always required during power-on. If the control signal from the MPU is HZ, an overcurrent may flow through the IC. A protection is required to prevent the HZ signal at the input pads during power-on. Be sure to initialize it by RES pad when turning on the power supply. When the reset command is used, only parameters 8 to 14 in the above initialization are executed.
16
NT7501
FR COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM2 COM7 COM1 COM0
COM8 COM9 COM10 COM11 COM12 COM13 COM14
SEG0
SEG1
COM0 ~ SEG0 COM15 SEG0 SEG1 SEG2 SEG3 SEG4
COM0 ~ SEG1
VDD VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0 V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0
Figure 7.
17
NT7501
COMMANDS The NT7501 uses a combination of A0, RD (E) and WR ( R W ) signals to identify data bus signals. As the chip analyzes and executes each command using the internal timing clock only, (regardless of external clock) its processing speed is very high and its busy check is usually not required. The 8080 series microprocessor interface enters read status when a low pulse is input to the RD pad and write status when a low pulse is input to the WR pad. The 6800 series microprocessor interface enters read status when a high pulse is input to the R W pad and write status when a low pulse is input to this pad. When a high pulse is input to the E pad, the command is activated. (For timing, see AC Characteristics.). Accordingly, in the command explanation and command table, RD (E) becomes 1(high) when the 6800 series microprocessor interface reads the status of display data. This is an only different point from the 8080 series microprocessor interface. Looking at the 8080 series, microprocessor interface example commands are explained below. When the serial interface is selected, input data in sequence starting from D7. Command Set 1. Display ON/OFF Alternatively turns the display on and off. A0 0 E RD 1 RW WR 0 1 0 1 0 1 1 1 D D7 D6 D5 D4 D3 D2 D1 D0
The display turns off when D goes low and it turns on when D goes high. 2. Set Display Start Line Specifies the line address (refer to Figure 4) to determine the initial display line, or COM0. The RAM display data becomes the top line of the LCD screen. It is followed by the higher number of lines in ascending order, corresponding to the duty cycle. When this command changes the line address, the smooth scrolling or page change takes place. A0 0 E RD 1 RW WR 0 0 1 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
A5 0 0 0
A4 0 0 0
A3 0 0 0 :
A2 0 0 0
A1 0 0 1
A0 0 1 0
Line address 0 1 2 :
1 1
1 1
1 1
1 1
1 1
0 1
62 63
18
NT7501
3. Set Page Address Specifies the page address where to load display RAM data in the page address register. Any RAM data bit can be accessed when its page address and column address are specified. The display remains unchanged even when the page address is changed. Page address 8 is the display RAM area dedicated to the indicator and only D0 is valid for data change. A0 0 E RD 1 RW WR 0 1 0 1 1 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
A3 0 0 0 0 0 0 0 0 1 4.
A2 0 0 0 0 1 1 1 1 0
A1 0 0 1 1 0 0 1 1 0
A0 0 1 0 1 0 1 0 1 0
Page address 0 1 2 3 4 5 6 7 8
Set Column Address Specifies the column address of the display RAM. Divide the column address into 4 higher bits and 4 lower bits. Set each of them in succession. When the microprocessor repeatedly access the display RAM, the column address counter is incremented during each access until address 132 is accessed. The page address is not changed during this time. A0 Higher bits Lower bits 0 0 E RD 1 1 RW WR 0 0 0 0 0 0 0 0 1 0 A7 A3 A6 A2 A5 A1 A4 A0 D7 D6 D5 D4 D3 D2 D1 D0
A7 0 0
A6 0 0
A5 0 0
A4 0 0 :
A3 0 0
A2 0 0
A1 0 0
A0 0 1
Column address 0 1 :
1
0
0
0
0
0
1
1
131
19
NT7501
5. Read Status A0 0 Busy: ADC: E RD 0 RW WR 1 BUSY ADC ON/OFF RESET 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0
ON/OFF: RESET: 6.
When high, the NT7501 is busy due to either internal operation or being reset. Any command is rejected until BUSY goes low. The busy check is not required if enough time is provided for each cycle. Indicates the relationship between RAM column address and segment drivers. When low, the display is reversed and the column address "100-n" corresponds to segment driver n. When high, the display is normal and column address corresponds to segment driver n. Indicates whether the display is on or off. When it goes low the display turns on. When it goes high, the display turns off. This is the opposite of Display ON/OFF command Indicates that initialization is in progress due to RES signal or by reset command. When low, the display is on. When high, the chip is being reset.
Write Display Data Write 8-bit data in the display RAM. As the column address is incremented by 1 automatically after each writing, the microprocessor can continue to write data of multiple words. A0 1 E RD 1 RW WR 0 Write data D7 D6 D5 D4 D3 D2 D1 D0
7.
Read Display Data Reads 8-bit data from the display RAM area specified by the column address and page address. As the column address is incremented by 1 automatically after each reading, the microprocessor can continue to read data of multiple words. A single dummy reading is required immediately after the column address setup. Refer to the display RAM section of FUNCTIONAL DESCRIPTION for details. Note that no display data can be read via the serial interface. A0 1 RD 0 WR 1 D7 D6 D5 D4 D3 D2 D1 D0
Read data
8.
ADC Select Changes the relationship between the RAM column address and the segment driver. The order of the segment driver output pads can be reversed by the software. This allows flexible IC layout during the LCD module assembly. For details, refer to the column address section of Figure4. When display data is written or read, the column address is incremented by 1 as shown in Figure4. A0 0 E RD 1 RW WR 0 1 0 1 0 0 0 0 D D7 D6 D5 D4 D3 D2 D1 D0
When D is low, the right rotation (normal direction) When D is high, the left rotation (reverse direction) 9. Normal/ Reverse Display Reverses the Display ON/OFF status without rewriting the contents of the display data RAM. E RW D7 D6 D5 D4 D3 D2 D1 D0 A0 RD WR 0 1 0 1 0 1 0 0 1 1 D
When D is low, the RAM data is high, being LCD ON potential (normal display) When D is high, the RAM data is low, being LCD ON potential (reverse display)
20
NT7501
10. Entire Display ON Forcibly turns the entire display on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This command has priority over the Normal/Reverse Display command. When D is low, the normal display status is provided. A0 0 E RD 1 RW WR 0 1 0 1 0 0 1 0 D D7 D6 D5 D4 D3 D2 D1 D0
When D is high, the Entire display ON status is provided. If the Entire Display ON command is executed during the display OFF status, the LCD panel enters Power Save mode. Refer to the Power Save section for details. 11. Set LCD Bias Selects a bias ratio for the voltage required for driving the LCD. This command is enabled when the voltage follower in the power supply circuit operates. A0 0 E RD 1 RW WR 0 1 0 1 0 0 0 1 D D7 D6 D5 D4 D3 D2 D1 D0
The potential V0 is resistively divided inside the IC to produce potentials V1, V2, V3 and V4 which are necessary to drive the LCD. The bias ratio can be selected using the LCD bias setting command. Moreover, the potentials V1, V2, V3 and V4 are converted in the impedance and supplied to the LCD drive circuit. Duty 1/33 Bias ratio of LCD power supply 1/5 bias or 1/6 bias
12. Read-Modify-Write A pair of Read-Modify-Write and End commands must always be used. Once a Read-Modify-Write is issued, the column address is not incremental by the Read Display Data command but incremented by the Write Display Data command only. It continues until the End command is issued. When the End command is issued, the column address returns to the address before the Read-Modify-Write was issued. This can reduce the microprocessor load when data of a specific display area is repeatedly changed during cursor blinking or others. A0 0 Note: E RD 1 RW WR 0 1 1 1 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0
Any command except Read/Write Display Data and Set Column Address can be issued during Read-ModifyWrite mode.
21
NT7501
Cursor display sequence
Set Page Address Set Column Address Read-Modify-Write Dummy Read Read Data
No
Write Data
Completed?
Yes
End
13. End Cancels the Read-Modify-Write mode and returns the column address to the original address (when Read-Modify-Write was issued.) A0 0 E RD 1 RW WR 0 1 1 1 0 1 1 1 0 D7 D6 D5 D4 D3 D2 D1 D0
Return Column address N N+1 N+2 N+3 N+m N End
Read-Modify-Write mode is selected
22
NT7501
14. Reset Resets the Initial Display Line register, Column Address counter, Page Address register, and output status selector circuit to their initial status. The Reset command does not affect the contents of the display RAM. Refer to the Reset circuit section of FUNCTION DESCRIPTION. A0 0 E RD 1 RW WR 0 1 1 1 0 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0
The Reset command cannot initialize the LCD power supply. Only the Reset signal to the RES pad can initialize the supply. 15. Output Status Select Register Applicable to the NT7501. When D is high or low, the scan direction of the COM output pad is selectable. Refer to the Output Status Selector Circuit in the FUNCTION DESCRIPTION for details. A0 0 E RD 1 RW WR 0 1 1 0 0 D * * * D7 D6 D5 D4 D3 D2 D1 D0
D : Selects the scan direction of COM output pad D = 0: Normal (COM0 COM31) D = 1: Reverse (COM31 COM0) *: Invalid bit 16. Set Power Control Selects one of eight power circuit functions using a 3-bit register. An external power supply and part of the on-chip power circuit can be used simultaneously. Refer to the Power Supply Circuit section of the FUNCTION DESCRIPTION for details. A0 0 E RD 1 RW WR 0 0 0 1 0 1 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
When A0 goes low, the voltage follower turns off. When A0 goes high, it turns on When A1 goes low, the voltage regulator turns off. When A1 goes high, it turns on When A2 goes low, the voltage booster turns off. When A2 goes high, it turns on 17. Set Electronic Control Adjusts the contrast of the LCD panel display by changing the V0 LCD drive voltage that is output by the voltage regulator of the on-board power supply. This command selects one of the 32 V0 LCD drive voltages by storing data in the 5-bit register. The V0 voltage adjusting range should be determined depending on the external resistance. Refer to the Voltage Regulator section of the FUNCTION DESCRIPTION for details. A0 0 A4 0 0 0 1 1 1 E RD 1 RW WR 0 A3 0 0 0 1 1 1 1 A2 0 0 0 : 1 1 1 0 1 1 1 0 1 High 0 A1 0 0 1 0 A4 A0 0 1 0 " A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
I V0 I LOW
Set register to (D4, D3, D2, D1, D1, D0) = (0, 0, 0, 0, 0) to suppress the electronic control function.
23
NT7501
18. Static Indicator This command turns on or off the static drive indicators. The indicator display is controlled by this command only, and it is not affected by the other display control commands. Either the FR or FRS terminal is connected to either of the static indicator LCD drive electrodes, and the remaining terminal is connected to another electrode. When the indicator is turned on, the static drive operates and the indicator blinks at an interval of approximately one second. This pattern separation between indicator electrodes and dynamic drive electrodes is recommended. A closer pattern may cause a LCD and electrode deterioration. A0 0 D 0: Static indicator OFF 1: Static indicator ON 19. Power Save (Compound Command) When all displays are turned on during display off, the Power Save command is issued to greatly reduce the current consumption. If the static indicators are off, the Power Save command sleeps the system. If on, this command stands by the system. Release the Sleep mode using the Power Save OFF command (Display ON command or Entire Display OFF command).
Static Indicator OFF Static Indicator ON
E RD 1
RW WR 0
D7 1
D6 0
D5 1
D4 0
D3 1
D2 1
D1 0
D0 D
Power Save (Display OFF and Entire Display ON)
(Sleep mode)
(Standby mode)
Power Save OFF (Display ON or Entire Displays OFF )
Static Indicator ON
(Sleep mode released)
(Standby mode released)
Sleep mode This mode stops every operation of the LCD display system, and can reduce current consumption to a nearly static current value if no access is made from the microprocessor. The internal status in the sleep mode is as follows: (1) Stops the oscillator circuit and LCD power supply circuit. (2) Stops the LCD drive and outputs the VSS level as the segment/common driver output. (3) Holds the display data and operation mode provided before the start of the sleep mode. (4) The MPU can access the built-in display RAM. Standby mode Stops the operation of the duty LCD display system and turns on only the static drive system to reduce current consumption to the minimum level required for static drive. The ON operation of the static drive system indicates that the NT7501 is in the standby mode. The internal status in the standby mode is as follows: (1) Stops the LCD power supply circuit. (2) Stops the LCD drive and outputs the VSS level as the segment/common driver output. However, the static drive system operates. (3) Holds the display data and operation mode provided before the start of the standby mode. (4) The MPU can access to the built-in display RAM. When the RESET command is issued in the standby mode, the sleep mode is set.
24
NT7501
When the LCD drive voltage level is given by an external resistive driver, the current of this resistor must be cut so that it may be fixed to the floating or VSS level, prior to, or concurrently with causing the NT7501 to go into the sleep mode or standby mode. When an external power supply is used, likewise, the function of this external power supply must be stopped so that it may be fixed to the floating or VSS level, prior to, or concurrently with causing the NT7501 series to go into the sleep mode or standby mode. 20. Test Command This is the dedicated IC chip test command. It must not be used for normal operation. If the Test command is issued unconsciously, set the RES input to low or issue the Reset command to release the test mode. E RD 1 RW WR 0 1 1 1 1 * * * *
A0 0 *: Invalid bit
D7
D6
D5
D4
D3
D2
D1
D0
Cautions: The NT7501 holds an operation status specified by each command. However, the internal operation status may be changed by a high level of ambient noise. Consideration must be given to suppressing the noise on the package and system and to preventing ambient noise. To prevent spike noise, built-in software for periodical status refreshment is recommended. The test command can be inserted in an unexpected place. Therefore it is recommended the user enter the test mode reset command F0h during the refresh sequence.
25
NT7501
Code Command A0 (1) Display ON/OFF (2) Set Display Start Line (3) Set Page Address (4) Set Column Address 4 higher bits (5) Set column Address 4 lower bits (6) Read Status (7) Write Display Data (8) Read Display Data 0 0 0 0 RD 1 1 1 1 WR 0 0 0 0 D7 1 0 1 0 D6 0 1 0 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 D Turns on the LCD panel when goes high, and turns it off when goes low Specifies the RAM display line for COM0 Sets the display RAM page in the Page Address register Sets the 4 higher bits of column address of the display RAM in register Sets the 4 lower bits of column address of the display RAM in register Reads the status information Writes data in the display RAM Reads data from the display RAM Sets the normal relationship between the RAM column address and the segment driver when low, but reverses the relationship when high Normal display when low, but reverse display when high Selects normal display (0) or Entire Display ON (1) Sets the LCD drive voltage bias ratio Increments the Column Address counter during each writing when high and during each reading when low Releases the Read-ModifyWrite Resets the internal functions Selects the COM output scan direction. * Invalid data Selects the power circuit operation mode Sets the V0 output voltage to Electronic Control register Set the static indicator On/Off 0: OFF 1: ON Compound command of display OFF and entire display ON IC Test command. Do not use! Command of test mode reset Function
Display start address 1 0 1 1 Page address Higher column address
0 0 1 1
1 0 1 0
0 1 0 1
0 Status
0
0
0
Lower column address 0 0 0 0
Write data Read data
(9) ADC select
0
1
0
1
0
1
0
0
0
0
D
(10) Normal/Reverse Display (11) Entire Display ON/OFF (12) Set LCD Bias
0 0 0
1 1 1
0 0 0
1 1 1
0 0 0
1 1 1
0 0 0
0 0 0
1 1 0
1 0 1
D D D
(13) Read-Modify-Write
0
1
0
1
1
1
0
0
0
0
0
(14) End (15) Reset (16) Set Output Status Register (17) Set Power Control (18) Set Electronic Control Register (19) Set static indicator On/Off (20) Power Save (21) Test Command (22) Test Mode Reset
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 0 1 1 1 1
1 1 1 0 0 0 1 1
1 1 0 1 0 1 1 1
0 0 0 0
1 0 D 1
1 0 *
1 1 *
0 0 *
Operation status
Electronic control value 0 1 1 1 * 0 1 * 0 0 * 0 D * 0
Note: Do not use any other command, or system malfunction may result.
26
NT7501
Absolute Maximum Rating*
DC Supply Voltage (VDD) . . . . . . . .. . -0.3V to + 6.0V DC Supply Voltage (VOUT, V0) . . . . . . -0.3V to + 10.5V Input Voltage . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Operating Ambient Temperature . . . -40C to + 85C Storage Temperature . . . . . . . . . .. -55C to + 125C ELECTRICAL CHARACTERISTICS DC Characteristics (VSS = 0V, VDD = 2.4 - 3.5V TA = -40 to 85C unless otherwise specified) Symbol Parameter Min. 2.4 VDD Operating Voltage 2.4 2.4 VOUT V0 VREG1 VREG2 IDD1 Booster output voltage Voltage regulator operation voltage Reference voltage 1 Reference voltage 2 Dynamic current consumption 1 Dynamic current consumption 2 Sleep mode current consumption Standby mode current consumption High-level input voltage 0.8 X VDD 6.0 5.0 2.0 2.25 2.2 2.45 22 Typ. Max. 3.5 3.0 2.4 9.0 8.0 2.4 2.65 35 Unit V V V V V V V A TA = 25C, TPS1, TPS0 = 0, 0 TA = 25C, TPS1, TPS0 = 0, 1 VDD = 3V, V0 = 8V, built-in power supply off, display on, display data = checker and no access, TA = 25C 3X boosting, VDD = 3V, V0 = 8V, built-in power supply on, display on, display data = checker and no access, TA = 25C During sleep, TA = 25C During standby, TA = 25C A0, D0 - D7, RD (E), WR ( R W ), CS , CS2, FR, M/S, C86, P/S and DOF VILC Low-level input voltage VSS 0.2 X VDD V A0, D0 - D7, RD (E), WR ( R W ), CS , CS2, FR, M/S, C86, P/S and DOF VOHC VOLC VIHS VILS High-level output voltage Low -level output voltage High-level input voltage Low-level input voltage 0.8 X VDD VSS 0.85 X VDD VSS VDD 0.2 X VDD VDD 0.15 X VDD V V V IOH = -0.5mA (D0 - D7, FR, FRS, DYO, DOF and CL) IOL = 0.5mA (D0 - D7, FR, FRS, DYO, DOF and CL) Schmitt trigger input (CL, SCL(D6), TPS0, TPS1 and RES ) Schmitt trigger input (CL, SCL(D6), TPS0, TPS1 and RES ) Triple boosting Quadruple boosting Condition
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
IDD2 ISP ISB VIHC
-
48 0.01 10
80 1 20 VDD
A A A V
27
NT7501
DC Characteristics (Continued) Symbol ILI IHZ Parameter Input leakage current HZ leakage current Min. -1.0 -3.0 Typ. Max. 1.0 3.0 Unit A A Condition VIN=VDD or VSS (A0, RD (E), WR ( R W ), CS , CS2, M/S, C86, P/S, TPS0, TPS1 and RES ) When the D0 - D7, FR, CL, DYO and DOF are in high impedance TA = 25C, These are the resistance values for when 0.1V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V1, V2, V3, V4)
RON
LCD driver ON resistance
3.0
4.5
k
V0 = 8.0V
CIN fOSC Notes:
Input pad capacity Oscillation frequency 18
5.0 22
8.0 26
pF kHZ
TA = 25C, f = 1MHz TA = 25C, VDD = 3.0V
1. Voltages V0 V1 V2 V3 V4 Vss must always be satisfied.
28
NT7501
AC Characteristics
(1) System Buses
A0 tAS8 tAH8
CS1
(CS2 = "1") tCYC8 tCCLW tCCLR
WR, RD
tCCHW tCCHR tDS8 tDS8
D0 - D7 (WRITE) tACC8 D0 - D7 (READ) tCH8
(VDD = 2.4 - 3.5V, TA = -40 - 85C) Symbol TAH8 TAS8 TCYC8 TCCLW TCCLR TCCHW TCCHR TDS8 TDH8 TACC8 TCH8 Parameter Address hold time Address setup time System cycle time Control L pulse width (WR) Control L pulse width (RD) Control H pulse width (WR) Control H pulse width (RD) Data setup time Data hold time RD access time Output disable time 10 Min. 0 0 400 55 125 180 130 35 13 125 90 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns CL = 100pF CL = 100pF Condition
29
NT7501
(2) System Buses
A0
R/W
tAS6
tAH6
CS
(CS2 = "1") tCYC6 E tEWHW tEWHR
tEWLW tEWLR tDS6 D0 - D7 (WRITE) tACC6 D0 - D7 (READ) tOH6 tDH6
(VDD = 2.4 - 3.5V, TA = -40 - 85C) Symbol TCYC6 TAS6 TAH6 TDS6 TDH6 TOH6 TACC6 TEWLR TEWLW TEWHR TEWHW Parameter System cycle time Address setup time Address hold time Data setup time Data hold time Output disable time Access time Enable Low pulse width Enable high pulse width 125 55 125 180 Min. 400 0 0 35 13 10 90 125 Typ. Max. Unit nS nS nS nS nS nS nS nS nS nS nS CL = 100pF CL = 100pF Condition
30
NT7501
(3) Serial Interface
CS1 (CS2 = "1")
tCSS
tCSH
tSAS
tSAH
A0 tSCYC SCL tSLW tSHW
tf tSDS
tr tSDH
SI
(VDD = 2.4 - 3.5V, TA = -40 - 85C) Symbol TSCYC TSHW TSLW TSAS TSAH TSDS TSDH TCSS TCSH Parameter Serial clock cycle Serial clock H pulse width Serial clock L pulse width Address setup time Address hold time Data setup time Data hold time CS1 serial clock time CS1 serial clock time Min. 450 180 135 90 360 90 90 55 180 Typ. Max. Unit nS nS nS nS nS nS nS nS nS Condition
31
NT7501
(4) Display Control Timing
CL (OUT)
tDFR FR
tDOH
tDOL
DYO
(VDD = 2.4 - 3.5V, TA = -40 - 85C) Symbol TDFR TDOH TDOL Parameter FR delay time DYO "H" delay time DYO "L" delay time Min. Typ. 13 55 55 Max. 70 180 180 Unit nS nS nS CL = 50pF Condition
(5) Reset Timing
tRW
RES
tR
Internal circuit status
During reset
End of reset
(VDD = 2.4 - 3.5V, TA = -40 - 85C) Symbol TR TW Parameter Reset time Reset low pulse width Min. 1.0 1.0 Typ. Max. Unit S S Condition
32
NT7501
MICROPROCESSOR INTERFACE (for reference only)
8080-series Microprocessors
VDD
Vcc
A0 A1 to A7 IORQ
A0 CS1 CS2
VDD
Decoder
C86
MPU
D0 to D7 RD WR RES GND RESET D0 to D7 RD WR RES
NT7501
VSS VDD
P/S VSS
VSS
6800-series Microprocessors
VDD
Vcc
A0 A1 to A15 VMA
A0 CS1 CS2
VDD VDD
Decoder
C86
MPU
D0 to D7 E R/W RES GND RESET D0 to D7 E R/W RES
NT7501
VDD P/S VSS
VSS
Figure 8
33
NT7501
Bonding Diagram
197 181
7310 m
180~113
114
98
198 200 211~199
NT7501
97
Y
95
(0,0)
X
1450 m
94~82
212 214 1 17 18~63
83 81 64 80
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Designation FRS FR DYO CL DOF VS1 M/S RES VSS P/S CS1 VDD CS2 C86 VSS A0 WR RD VDD VDD VDD VDD VDD VDD VDD VDD D0 D1 D2 D3
X -3357.5 -3272.5 -3187.5 -3102.5 -3017.5 -2932.5 -2847.5 -2762.5 -2677.5 -2592.5 -2507.5 -2422.5 -2337.5 -2252.5 -2167.5 -2082.5 -1997.5 -1912.5 -1827.5 -1742.5 -1657.5 -1572.5 -1487.5 -1402.5 -1317.5 -1232.5 -1147.5 -1062.5 -977.5 -892.5
Y -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655
Pad No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Designation D4 D5 D6 D7 VSS VSS VSS VSS VSS VSS VSS VSS VOUT VOUT CAP3+ CAP3+ CAP1CAP1CAP1+ CAP1+ CAP2CAP2CAP2+ CAP2+ V0 V0 VR VR VSS VSS
X -807.5 -722.5 -637.5 -552.5 -467.5 -382.5 -297.5 -212.5 -127.5 -42.5 42.5 127.5 212.5 297.5 382.5 467.5 552.5 637.5 722.5 807.5 892.5 977.5 1062.5 1147.5 1232.5 1317.5 1402.5 1487.5 1572.5 1657.5
Y -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655
34
NT7501
Bonding Diagram (continued)
Pad No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Designation VDD VDD V0 V0 V1 V1 V2 V2 V3 V3 V4 V4 VSS VSS TPS0 TPS1 VDD OP1 OP2 OP3 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS SEG0 SEG1 SEG2 X 1742.5 1827.5 1912.5 1997.5 2082.5 2167.5 2252.5 2337.5 2422.5 2507.5 2592.5 2677.5 2762.5 2847.5 2932.5 3017.5 3102.5 3187.5 3272.5 3357.5 3590 3590 3590 3590 3590 3590 3590 3590 3590 3590 3590 3590 3590 3590 3590 3590 3590 3465 3395 3325 Y -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -655 -648.1 -578.1 -508.1 -438.1 -368.1 -298.1 -228.1 -158.1 -88.1 -18.1 51.9 121.9 191.9 261.9 331.9 401.9 471.9 655 655 655 Pad No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 139 139 140 Designation SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 X 3255 3185 3115 3045 2975 2905 2835 2765 2695 2625 2555 2485 2415 2345 2275 2205 2135 2065 1995 1925 1855 1785 1715 1645 1575 1505 1435 1365 1295 1225 1155 1085 1015 945 875 805 735 665 595 525 Y 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655
35
NT7501
Bonding Diagram (continued)
Pad No. 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 Designation SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 X 455 385 315 245 175 105 35 -35 -105 -175 -245 -315 -385 -455 -525 -595 -665 -735 -805 -875 -945 -1015 -1085 -1155 -1225 -1295 -1365 -1435 -1505 -1575 -1645 -1715 -1785 -1855 -1925 -1995 -2065 -2135 Y 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 Pad No. 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 Designation SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COMS X -2205 -2275 -2345 -2415 -2485 -2555 -2625 -2695 -2765 -2835 -2905 -2975 -3045 -3115 -3185 -3255 -3325 -3395 -3465 -3590 -3590 -3590 -3590 -3590 -3590 -3590 -3590 -3590 -3590 -3590 -3590 -3590 -3590 -3590 -3590 -3590 Y 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 655 471.9 401.9 331.9 261.9 191.9 121.9 51.9 -18.1 -88.1 -158.1 -228.1 -298.1 -368.1 -438.1 -508.1 -578.1 -648.1
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NT7501
Package Information
A1 B3 100 n m C5 99 A2
A1 B3
C2 C1 r 16 C3 17 m n m n n
m
C2 C1 r
NT7501
n m C5
16 17 m n m n
C3
C4 B4 B1 79 B2
C4 80 n m B4 B1
Chip Outline Dimensions
unit:m
Symbol A1 A2 C1 C2 C3 C4 C5
Dimensions in m 169 70 232.1 120 70 55.9 25
Symbol B1 B2 B3 B4 m n r
Dimensions in m 276.5 85 30 20 90 42 35
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